What is FPGA XDC?

 An FPGA XDC is a Xilinx Design Constraints file (extension .xdc) used in Vivado to tell the tools how your design must be connected and timed.

Think of it as the “rules + wiring map” for implementation.

What an XDC file contains

1) Pin assignments (physical I/O mapping)

Maps your top-level ports to FPGA package pins and sets I/O standards.

Example:

set_property PACKAGE_PIN W5 [get_ports {clk}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk}]

2) Timing constraints (so timing analysis is correct)

Defines clocks and timing relationships.

Example:

create_clock -period 10.000 [get_ports clk]   ;# 100 MHz

You can also constrain:

• input/output delays (set_input_delay, set_output_delay)

• clock uncertainty, generated clocks, false paths, multicycle paths, etc.

3) I/O electrical constraints

Sets things like:

• IOSTANDARD (LVCMOS33, LVDS, SSTL, etc.)

• drive strength (DRIVE)

• slew rate (SLEW FAST/SLOW)

• pullups/pulldowns (PULLUP, PULLDOWN)

4) Other implementation constraints

Such as:

• placement constraints (Pblocks, LOCs)

• special routing constraints

• debug core constraints (ILA/VIO-related sometimes)

Why XDC matters

Without a correct XDC:

• your signals may go to the wrong pins (board won’t work)

• clocks may be unconstrained → timing report is meaningless

• you can get I/O standard mismatches (risking damage or non-function)

Where to get the right XDC

• Your FPGA board vendor usually provides a master XDC (all pins defined).

• You copy the needed lines and match them to your top-level port names.

Common pitfalls

• Port name mismatch: XDC references get_ports {clk} but your top port is sys_clk.

• Forgetting create_clock: leads to “no clocks” / “unconstrained paths.”

• Wrong IOSTANDARD (e.g., using 3.3V when bank is 1.8V).

• Assigning pins in the wrong bank or using reserved pins.