Detailed Discussion on IIC Communication Protocol of FPGA
“IIC” and “I²C” are the same 2-wire serial bus. In an FPGA you typically implement it as a bit-accurate state machine plus open-drain bidirectional I/O control . Below is a detailed, practical discussion (master + slave), with the stuff that usually trips people up. 1) I²C fundamentals (what the bus really is) Two wires, open-drain, “wired-AND” SCL = clock SDA = data Devices never drive a ‘1’ . They either: drive low (0) , or release the line (Z) so an external pull-up resistor makes it high. Because low is dominant, multiple devices can share the bus safely. Start/Stop are special conditions (not “bytes”) START (S): SDA goes 1→0 while SCL is high STOP (P): SDA goes 0→1 while SCL is high Repeated START (Sr): a START without a STOP in between (common for register reads) Data validity rule (the golden rule) SDA must be stable when SCL is high SDA is allowed to change only when SCL is low Receiver samples SDA on SCL rising edge...