Detailed explanation of the power on process of lattice FPGA
Here's a detailed technical breakdown of the power-on process for Lattice FPGAs (using iCE40 , ECP5 , or MachXO families as reference): Lattice FPGA Power-On Sequence The boot process involves multiple hardware and firmware-controlled stages: 1. Power Rail Stabilization Required Voltage Rails (typical): Core Voltage (VCC) : 1.2V (ECP5) / 1.0V (iCE40) I/O Voltage (VCCIO) : 1.8V/2.5V/3.3V (bank-dependent) Auxiliary Voltage (VCCAUX) : 2.5V/3.3V (for PLLs, configuration logic) Power Sequencing : Option 1 : Monolithic ramp (all rails together) Option 2 : Staggered (VCCAUX → VCC → VCCIO) Critical : Must meet datasheet timing (e.g., ECP5 requires VCC within 50ms of VCCAUX) 2. Reset and Configuration Phase A. Power-On Reset (POR) Circuit Internal POR circuit monitors: All voltage rails Clock stability (if external oscillator used) POR Timeout : Typically 100-300ms (device-specific) Reset States : Cold Reset : Full reconfiguration Warm Reset : Partial reconfiguration (if supported...