How to design a microcontroller PCB in Altium?
Here’s a practical, Altium-first workflow to design a microcontroller PCB (from “empty project” to “ready for fabrication”), with the checks that prevent 90% of first-rev pain.
1) Start with requirements (so the schematic is correct)
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MCU part number + package (QFN/LQFP/BGA)
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Power rails (1.8/3.3/5V), max current, ADC reference needs
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Clocking (internal RC ok? need crystal?)
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Programming/debug (SWD/JTAG/USB-UART/boot pins)
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Interfaces (I²C/SPI/UART/CAN/USB), connector types
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Environment (ESD, EMI, automotive? temperature?)
2) In Altium: create a clean project structure
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File → New → Project → PCB Project
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Add:
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Schematic (
.SchDoc) -
PCB (
.PcbDoc)
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Set units, grids, and templates early (keeps footprint placement sane).
3) Build or verify your libraries (critical)
You need:
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Schematic symbol
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Footprint
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3D model (optional but helpful)
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Pin mapping correct (power pins, SWD, BOOT, NRST)
Best practice:
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Prefer manufacturer/Altium verified libs when possible.
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If you make your own footprint: verify pad sizes, pitch, courtyard, paste mask, and pin-1 marker against the datasheet.
4) Schematic design: microcontroller “minimum system” blocks
A) Power (must be done right)
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Decoupling caps: typically 0.1 µF per VDD pin + 1–10 µF bulk near MCU.
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Analog supply (VDDA/VREF): filter with ferrite bead or small resistor + cap (per datasheet).
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Add power LED and test points (VIN, 3V3, GND, NRST, SWDIO, SWCLK).
B) Reset + boot straps
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NRST: pull-up (commonly 10k) + optional RC (if recommended).
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BOOT0/BOOT1 pins: pull-down/up per your boot strategy, add header/jumper if you’ll need recovery.
C) Clocking
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If using a crystal: place load caps exactly as datasheet recommends; keep routing short/symmetric.
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If internal oscillator is enough, skip crystal for cost and simplicity.
D) Programming / Debug
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Add SWD header (2x5 1.27mm Cortex Debug or 1x4/1x6 custom):
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SWDIO, SWCLK, NRST, GND, 3V3, (optional SWO)
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If using USB: add ESD protection + correct impedance routing (see below).
E) I/O protection and connectors
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Put ESD diodes at external connectors (USB, buttons, long cables).
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Series resistors (22–47Ω) on fast edges (SPI SCK, USB FS signals, etc.) can help ringing/EMI.
5) Convert to PCB and define rules
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Design → Update PCB Document from schematic.
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Set:
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Board shape
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Layer stack (2-layer vs 4-layer)
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Design Rules: trace width/clearance, via sizes, differential pairs (USB), solder mask rules.
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If you can afford it: 4-layer makes MCU boards much easier (solid GND plane, cleaner EMI).
6) Placement (most important physical step)
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Place MCU first.
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Place decoupling capacitors:
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as close as physically possible to each power pin
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short trace to VDD pin, short via to GND plane
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Keep crystal + caps very close and away from noisy switching nodes (buck SW node).
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Put debug header at edge of board for easy access.
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Put connectors where cables make mechanical sense.
7) Routing guidelines (quick but high-impact)
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Ground: use an unbroken ground plane if possible. Don’t split GND unless you really know why.
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Power: short/wide traces for VDD rails; avoid daisy-chaining sensitive analog supplies.
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Clock/crystal: keep short, no vias if possible, guard with ground.
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USB (if used):
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route D+/D− as a differential pair
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keep them length-matched and away from noisy power switching
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follow your board stack’s impedance if you can; otherwise keep short and consistent
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Add stitching vias around edges / near connectors (helps EMI).
8) ERC/DRC + sanity checks (do not skip)
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Schematic ERC: unconnected power pins, wrong net labels, missing pull-ups.
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PCB DRC: clearance, solder mask slivers, unrouted nets.
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Check:
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pin 1 orientation on footprint
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decoupling caps actually connected to correct VDD pins
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SWD header pinout matches your programmer
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BOOT and reset resistors match your intended boot mode
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9) Output manufacturing files
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Gerbers / ODB++, NC Drill
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BOM
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Pick-and-place/CPL
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Assembly drawings (optional but helpful)

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