How to set up a pull up pin to high and low in FPGA?

 You don’t actually set the pull-up itself “high or low” — you either let the pull-up win (high) or override it by driving low.

Let’s break it down in FPGA terms.

---

1. What a “pull-up pin” really is

A pull-up (internal or external resistor to VCC) makes the pin:

• HIGH by default (when nothing is driving it),

• but still allows something to pull it LOW (switch, another device, or your FPGA output).

So for a pull-up pin you usually have these modes:

• Input with pull-up → used for buttons, open-collector signals, etc.

• Open-drain / open-collector style output with pull-up → used for shared lines (I²C-like).

You control HIGH/LOW by either:

• Releasing the pin (high-impedance Z) → pull-up makes it HIGH

• Actively driving 0 → forces it LOW

---

2. HDL pattern: open-drain pin with pull-up

Say you have an I/O pin io_line with a pull-up (internal or external).
In Verilog:

// Top-level port
inout wire io_line;

reg drive_low;   // 1 = pull line low, 0 = release line
wire line_in;

// Drive logic: 0 or Z (never drive 1 against a pull-up!)
assign io_line = drive_low ? 1'b0 : 1'bz;

// Read back the line level
assign line_in = io_line;

• To get LOW on the pin:
  drive_low <= 1'b1; → FPGA drives 0.

• To get HIGH on the pin:
  drive_low <= 1'b0; → FPGA drives Z, pull-up pulls it to 1.

Important: With a pull-up, you normally do not drive 1, you either drive 0 or Z. That’s how open-drain works and avoids bus fights.

---

3. Input with pull-up (e.g. button to GND)

If the pin is only an input:

• You configure the pin as input with pull-up in your constraints / tool.

• In HDL it’s just:

  input wire btn;  // has pull-up in constraints
  

• Externally:

  • btn → button → GND

  • When button not pressed → pull-up makes btn = 1

  • When button pressed → GND pulls btn = 0

You don’t “set” it high or low in HDL; you read it and the external circuit decides the level against the pull-up.

---

4. Where you actually turn on the pull-up

This is vendor/tool specific and not done by assigning 1/0 in HDL.

Xilinx (Vivado) example

In the .xdc constraint file:

set_property PACKAGE_PIN W5      [get_ports io_line]
set_property IOSTANDARD LVCMOS33 [get_ports io_line]
set_property PULLUP TRUE         [get_ports io_line]

Or instantiate the PULLUP primitive (older flows).

Intel / Altera (Quartus) example

Use the Assignment Editor or .qsf:

set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to io_line

(Exact name can vary by family, but it’s something like “weak pull-up resistor”.)

Lattice / others

Similar: in the pin constraints or via pin property dialog (“Pull-Up enable”).

---

5. Quick mental recipe

To use a pull-up pin in an FPGA:

1. Enable pull-up for that pin in the constraints (or add an external resistor).

2. Decide if the pin is:

   • Input → just read it, external circuitry pulls low.

   • Open-drain I/O → use inout and drive 0/Z in HDL.

3. Logic for HIGH/LOW:

   • HIGH = tri-state (Z) → pull-up wins.

   • LOW = drive 0.