How does FPGA implement AXI Lite interface?
AXI4-Lite is the “simple, memory-mapped” subset of AXI: no bursts, one beat per transaction, at most one outstanding per direction, no IDs . Implementing it in an FPGA usually means building a tiny register file that the CPU can read/write. Below is a compact, production-ready AXI4-Lite slave you can drop into your design (32-bit data, word-aligned addresses). It handles byte strobes, correct handshakes, and OKAY responses. What you implement Five channels (slave side, S_AXI_* ): Write address : AWADDR, AWVALID → AWREADY Write data : WDATA, WSTRB, WVALID → WREADY Write response : BRESP, BVALID ← BREADY Read address : ARADDR, ARVALID → ARREADY Read data/resp : RDATA, RRESP, RVALID ← RREADY Rules (AXI-Lite): Accept a write only when both AW and W fire (address and data are independent but you can require them to handshake in the same cycle). After the write, return BRESP=OKAY with BVALID until BREADY . For reads, handshake AR , then present RDATA ...
