What is FPGA XDC?
An FPGA XDC is a Xilinx Design Constraints file (extension .xdc ) used in Vivado to tell the tools how your design must be connected and timed . Think of it as the “rules + wiring map” for implementation. What an XDC file contains 1) Pin assignments (physical I/O mapping) Maps your top-level ports to FPGA package pins and sets I/O standards. Example: set_property PACKAGE_PIN W5 [get_ports {clk}] set_property IOSTANDARD LVCMOS33 [get_ports {clk}] 2) Timing constraints (so timing analysis is correct) Defines clocks and timing relationships. Example: create_clock -period 10.000 [get_ports clk] ;# 100 MHz You can also constrain: input/output delays ( set_input_delay , set_output_delay ) clock uncertainty, generated clocks, false paths, multicycle paths, etc. 3) I/O electrical constraints Sets things like: IOSTANDARD (LVCMOS33, LVDS, SSTL, etc.) drive strength ( DRIVE ) slew rate ( SLEW FAST/SLOW ) pullups/pulldowns ( PULLUP , PULLDOWN ) 4) Ot...